1. Field of the Invention
The present invention relates to a PLL (Phase-Locked Loop) circuit and, more particularly, to a reproduction PLL circuit used to reproduce an information signal which is converted into a digital signal and recorded on a recording medium such as a tape, a card, or a disk.
2. Description of the Prior Art
Conventionally, a PLL circuit for reproducing an information signal recorded as a digital signal is used to generate a reference clock for reading the recorded digital data. Especially, for a digital signal with change points generated at irregular time intervals, the edge of the digital signal is extracted to generate a pulse signal. By using the spectral component of the repetitive frequency of the pulse signal, a clock can be generated as a continuous pulse signal.
First, problems of a PLL circuit will be described with reference to the block diagram in FIG. 1 showing a well-known conventional PLL circuit of the first prior art.
The PLL circuit shown in FIG. 1 comprises a phase comparator 1201 for outputting a phase error signal proportional to the phase difference between a reference signal and a signal to be compared, a charge pump 1202 for receiving the phase error signal and outputting a current corresponding to the phase error signal, a loop filter 1203 which smoothes the output signal from the charge pump to output a control signal, and serves as an important circuit element for determining the circuit arrangement, the order, and the response characteristics of the PLL circuit, a VCO (Voltage-Controlled Oscillator) 1204 as an oscillator whose output frequency changes depending on the control signal from the loop filter 1203, and a frequency divider 1205 for dividing the output frequency from the VCO 1204.
To realize a short pull-in time in this PLL circuit, the loop gain must be increased to obtain a higher response speed. Once a signal is locked, the PLL circuit must be prevented from being oversensitive to not only normal noise but also noise due to a signal defect to stabilize the PLL circuit. For this purpose, once the PLL circuit is locked, the loop gain must be lowered to lower the response speed.
Generally, the following methods are used to lower the response speed of the PLL circuit.
(1) The gain constant of the phase comparator 1201 is lowered. PA1 (2) The output current from the charge pump 1202 is decreased. PA1 (3) The dumping factor of the loop filter 1203 is increased. PA1 (4) The bandwidth of the loop filter 1203 is narrowed. PA1 (5) The F-V (frequency-voltage) conversion gain constant of the VCO 1204 is lowered.
A PLL circuit for self-clocking, which extracts a clock from a signal recorded on a recording medium such as a magnetic tape or a CD, is disclosed in Japanese Unexamined Patent Publication No. 4-162263.
FIG. 2 is a block diagram of the PLL circuit according to the above second prior art. Referring to FIG. 2, a phase comparator 1301, a loop filter 1303, and a VCO 1304 can be regarded as the same as the phase comparator 1201, the loop filter 1203, and the VCO 1204 of the PLL circuit shown in FIG. 1.
As a characteristic feature of the second prior art, two charge pumps having the same characteristics, i.e., a first charge pump 1302a and a second charge pump 1302b are used.
A monostable multivibrator 1308 is a circuit for outputting a signal of high level for a predetermined period after the rise of a read gate signal. The output signal from the monostable multivibrator 1308 is used to open the gates of AND circuits 1309 and 1310.
The operation of the PLL circuit shown in FIG. 2 will be described next.
The reproduction signal is reproduced from an information recording medium (not shown) such as an optical disk. The read gate signal is generated by a controller (not shown). The read gate signal is output to a switch 1311 and used as a signal for switching a signal S1 to be input to the phase comparator 1301 between the reproduction signal and a predetermined reference clock.
Upon receiving the read gate signal, the monostable multivibrator 1308 outputs a signal S2 which goes high for a predetermined period T after the rise of the read gate signal to the AND circuits 1309 and 1310. The gates of the AND circuits 1309 and 1310 are open for the predetermined period T, so a phase lead signal and a phase lag signal from the phase comparator 1301 are output to the second charge pump 1302b through the AND circuits 1309 and 1310, respectively.
For the period T when the output signal S2 from the monostable multivibrator 1308 is at high level, both the first charge pump 1302a normally operating and the second charge pump 1302b simultaneously operate. For this reason, the sum of the output currents from the first charge pump 1302a and the second charge pump 1302b is twice larger than the output current from the first charge pump 1302a. This increases the loop gain of the PLL circuit, so the response speed of the PLL circuit can be made high. To lower the response speed from this state, the signal S2 is set at low level such that only the first charge pump 1302a can operate.
For this PLL circuit, however, the read gate signal must be generated by the controller outside the PLL circuit. For this reason, this PLL circuit cannot be used to extract a clock from a reproduction signal in a format which has no VFO or AM (Address Mark) pattern and therefore cannot set the read gate interval.
In addition, to set a number of loop gains, a corresponding number of charge pumps must be prepared, resulting in an increase in circuit scale.
A PLL circuit technique of maintaining stability of the PLL loop in a wide band or advancing the lock-up time by controlling the conversion gain of the VCO in the PLL loop in accordance with a desired frequency is disclosed in Japanese Unexamined Patent Publication No. 5-37370.
FIG. 3 is a block diagram of a PLL circuit according to the above third prior art. This conventional PLL circuit comprises a phase comparator 1401 for detecting the phase difference between a signal Fout/N divided by a first programmable frequency divider 1404 and a reference clock f output from a reference oscillator 1407 and outputting a phase error signal, a low-pass filter 1402 for smoothing the phase error signal, a VCO 1403 whose oscillation frequency changes depending on the output signal from the low-pass filter 1402, a second programmable frequency divider 1408 for dividing the output frequency from the VCO 1403, and the first programmable frequency divider 1404 for frequency-dividing the output signal from the second programmable frequency divider 1408.
The operation of the PLL circuit will be described next.
An output signal Fout from the second programmable frequency divider 1408, which is obtained by frequency-dividing the output signal from the VCO 1403 by M is frequency-divided by N by the first programmable frequency divider 1404 and then compared with the reference clock f by the phase comparator 1401. The PLL loop operates such that the phase difference between the reference clock f and the signal Fout/N becomes zero. For this reason, the relationship Fout=N.multidot.f holds.
A loop gain G of the PLL circuit is given by G=Kd.multidot.Fo.multidot.Ko/(MN) where Kd is the conversion gain of the phase comparator 1401, Fo is the conversion gain of the low-pass filter 1402, Ko is the conversion gain of the VCO, and N and M are the frequency division ratios of the first and second programmable frequency dividers 1404 and 1408, respectively.
In this prior art, in the control using the constant values M and N, the conversion gain of a first voltage-controlled oscillation circuit 1409 can be controlled by sending a control signal to the first voltage-controlled oscillation circuit 1409. Since the loop gain can be set at a desired value in accordance with the output frequency, the operation can be stabilized in a wide band.
This PLL circuit can be effectively used to obtain the output signal Fout N times larger than the reference signal f. However, the PLL circuit is not suitable for the purpose of self-clocking of extracting a clock from the recorded digital data itself. Especially, when recorded data has change points at irregular time intervals, the clock cannot be extracted.
More specifically, as the timing signal for reading data, the signal to be compared (reference signal f) input to the phase comparator 1401 is used, and no frequency divider can be arranged on the output side of the reference signal f. That is, the frequency division ratio cannot be determined using a circuit arrangement not associated with the output frequency.
Additionally, in use of a predetermined reference signal, when the frequency division ratio of the programmable frequency divider becomes high, the oscillation frequency of the VCO 1403 rises accordingly. Since Ko/(MN) in the loop gain G=Kd.multidot.Fo.multidot.Ko/(MN) does not change, the loop gain of the PLL circuit as a whole does not change.
Furthermore, addition of programmable frequency dividers undesirably increases the circuit scale. To finely set the frequency division ratio, the frequency division ratio increases, and accordingly, the oscillation frequency of the VCO 1403 must rise. In this case, the VCO is difficult to design, and various problems are posed, i.e., the current consumption of the VCO 1403 increases, or the oscillation output enters the circuit as noise.
A PLL circuit having an improved resistance to noise in the phase circuit and a short pull-in time is disclosed in Japanese Unexamined Patent Publication No. 7-302072. This PLL circuit has a lock-out detection means and uses a gate means for passing a reproduction signal only within an interval including the input synchronization signal detection edge timing.
In this PLL circuit, the capture range is determined by the edge timing interval. When the window width of the edge timing interval is within the range of N% before and after the edge, the capture range is maximized at N%, so the capture range cannot be increased.
For the PLL circuit disclosed in Japanese Unexamined Patent Publication No. 4-162263, the read gate signal must be generated by the controller outside the PLL circuit. For this reason, this PLL circuit cannot extract a clock from a reproduction signal in a format which cannot set the read gate interval.
In addition, to set a number of gains, a corresponding number of charge pumps must be prepared, resulting in an increase in circuit scale.
The PLL circuit disclosed in Japanese Unexamined Patent Publication No. 5-37370 can hardly be used for the purpose of self-clocking of extracting a clock from the recorded digital data itself. Especially, when recorded data change points at irregular time intervals, the clock cannot be extracted.
Additionally, in use of a predetermined reference signal, when the frequency division ratio of the programmable frequency divider becomes high, the oscillation frequency of the VCO 1403 rises accordingly. Since Ko/(MN) in the loop gain G=Kd.multidot.Fo.multidot.Ko/(MN) does not change, the loop gain of the PLL circuit as a whole cannot be changed.
Furthermore, addition of programmable frequency dividers undesirably increases the circuit scale. To finely set the frequency division ratio, the frequency division radio increases, and accordingly, the oscillation frequency of the VCO 1403 must rise. In this case, the VCO is difficult to design, and various problems are posed, i.e., the current consumption of the VCO 1403 increases, or the oscillation output enters the circuit as noise.
The PLL circuit disclosed in Japanese Unexamined Patent Publication No. 7-302072 has an arrangement in which an edge timing interval is inserted, and the reproduction signal passes only in this interval. Since this arrangement cannot follow a signal having jitter larger than the edge interval, the recorded signal cannot be read. For this reason, considerable limitations are imposed on the capture range or the conversion gain of the phase comparator in terms of system configuration.